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Description:
nSys Design Systems Pvt. Ltd.
nSys Verification Suite family is the world's largest portfolio of Verification IPs. Global leaders in Semiconductor, System Houses, Networking & Storage industries use our products to accelerate their ASIC/SoC designs. We have offices in Delhi & CA.
Trainee Electronics Engineer
Fresh Electronics Engineers will be provided on-the-job training for one year & will be part of the team responsible for enhancing the world's largest portfolio of Verification IPs.
- Students from good engineering colleges
- Minimum 70% in BE, XII & X
- Sound Digital Design fundamentals & knowledge of microprocessors is essential
- Knowledge of Verilog, C/C++ and OO concepts is preferred
Fresh Electronics Engineer from DCE/NSIT/NITs only
Fresh Electronics Engineers after training will be part of the team responsible for enhancing the world's largest portfolio of Verification IPs. You will work from specs and take the design through HDL coding, testing and release to customers.
- Students from DCE/NSIT/NIT only
- Excellent academic track record (min 75%)
- Sound Digital Design fundamentals & knowledge of microprocessors is essential
- Knowledge of Verilog, C/C++ and OO concepts is preferred
Address:
nSys Design Systems Pvt. Ltd.
B-09, 707 ITL Twin Tower
Netaji Subhash Place
Pitampura
NEW DELHI, India 110034
Email : hr@nsysinc.com
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